Nonlinear ternary decoder

ABSTRACT

THE NONLINEAR CHARACTERISTIC OF THE DECODER IS APPROXIMATED BY A PLURALITY OF DIFFERENTLY SLOPED STRAIGHT LINE SEGMENTS AND EACH TERNARY CONDITION IS REPRESENTED BY A DIFFERENT PAIR OF BINARY DIGITS. A FIRST SIGNAL, PRODUCED BY THE MOST SIGNIFICANT TERTIARY DIGITS OF A CODE GROUP, INDICATES THE MINIMUM VOLTAGE OF THE SEGMENT CONTAINING THE CODE GROUP. A SECOND SIGNAL, PRODUCED IN RESPONSE   TO AT LEAST THE LEAST SIGNIFICANT DIGITS OF THE CODE GROUP, INDICATES THE POSITION OF THE CODE GROUP ALONG SAID SEGMENTS. A WEIGHTING AND SUMMING CIRCUIT RESPONDS TO THESE TWO SIGNALS TO PRODUCE THE DECODER OUTPUT.

Feb. 2, 1971 AVlGNON EI'AL 3,560,960

NONLINEAR TERNARY DECODER Filed Dec. 22. 1967 3 Sheets-Sheet 1 InventorsMICHEL L. AV/CNOIV JOSE PH L. MAOER By W 0.1%

Agent M. L. AVIGNON E AL 3,560,960 NONLINEAR TERNARY DECODER Feb. 2,1971 3 Sheets-Sheet 2 Filed Dec. 22, 1967 1.. I Q wwwm 1 MIC/{4 t.AVIS/VON 0056? l. MAOER QC *5 @S a----kh i----:::.--.

United States Patent 3,560,960 NONLINEAR TERNARY DECODER Michel L.Avignon, Neuilly-sur-Seine, France, and Joseph L. Mader, Dietlikon,Switzerland, assignors to International Standard Electric Corporation,New York, N.Y., a corporation of Delaware Filed Dec. 22, 1967, Ser. No.692,929 Claims priority, application; France, Dec. 29, 1966, 89 3 4 Int.c1. H03k 13/02 US. Cl. 340-347 Claims ABSTRACT OF THE DISCLOSUREBACKGROUND OF THE INVENTION This invention relates to a digital decoderand more particularly to a nonlinear ternary decoder for translating aternary code number or code group into an analog quantity represented bythe code group.

In the ternary number base system, a digit of a given rank can have oneof the conditions 0, 1 and 2 which are represented in coded form bymeans of two binary bits. Thus, in one well known form of ternary code,referred to as code A these three ternary conditions or values arerespectively represented by the pair of binary bits ()1, 00, and 10.

Nonlinear decoders for binary codes using a resistor network andpermitting the achievement of a hyperbolic nonlinear characteristic isknown in the art. These resistors, the extreme values of which are inthe 2 ratio, must be switched according to the value of the number to bedecoded. However, it is known that every resistor has a given reactancethat is related to its value. If the switching frequency is high, theeffect of this reactance becomes important and the value ofcorresponding complex impedance depends on the number to be decoded. Itis, therefore, understood that a decoder comprising resistors the valuesof which are so dissimilar is quite difficult to realize and cannot havegreat precision.

Moreover, when an electronic switch is used to sample the signal to becoded, the switch presents, when it is on, a serial resistance(saturation resistance in the case of a transistor), that is notnegligible with regard to the network resistances of low value and thatintroduces a new source of errors.

To overcome the difficulty in obtaining a continuous nonlinearcharacteristic there has been described in US. Pat. No. 3,298,017 abinary number decoder so designed that its characteristic curvecomprises a succession of straight segments with different slopes, theseslopes being 3,560,960- Patentecl Feb. 2, 1971 chosen, for example, sothat the characteristic approximates a logarithmic curve.

The operation of this decoder is as follows, assuming that the number ofcodes which are applied to it comprise n=7 digits and that the voltagescorresponding to codes 0 and 2 -1 are respectively equal to 0 and Edvolts, the codes 2 1 and 2 being situated on both sides of the voltageEd/ 2 which characterizes the average value of the signal in the casewhen the codes represent periodic voltages. Each of these voltage rangesof Ed/2 amplitude is divided into three coding zones C1, C2, C3, towhich correspond respectively thirty-two, sixteen and sixteen codes andin which the values of the quantizing steps are different. Thus, in theC1 zone, which corresponds to the lowest voltages in absolute value onboth sides of the origin, the value of this quantizing step is equal toV. In the C2 zone, the quantizing step is equal to 8V volts and in theC3 zone, the quantizing step is equal to 64V volts. The characteristiccurve so determined comprises six segments, the slopes of which areproportional to the different values of the quantizing steps.

To obtain the analog voltage corresponding to a given binary codenumber, the zone to which this code number belongs is first determinedby the three most significant digits since each zone comprises a numberof codes equal to an integer power of two. The zone signal thus obtainedis used on one hand to generate a base or pedestal voltage equal to thevoltage that corresponds to minimum code of the zone and on the otherhand to generate a position voltage representing the position of thecode in the zone to which it belongs. This latter voltage is obtained bydecoding in a linear manner the least significant digit with a weightingcorresponding to the value of the quantizing step in this zone. Thesetwo voltages are then added together to obtain the analog voltagerepresented by the code.

SUMMARY OF THE INVENTION An object of the present invention is toprovide a nonlinear decoder for ternary numbers represented by twobinary digits per ternary rank or digit.

The decoder of the present invention operates in a manner similar to thebinary decoder described hereinabove under the section entitledBackground of the Invention. In the ternary decoder of the presentinvention the decoded voltage is obtained by the addition of a pedestalvoltage to a position voltage. The number of codes and also the slopesand the different zones or straight line segments representing thenonlinear characteristic are equal to an integer power of three.

It will be noticed that, in the coding of speech signals, the ternarycode employed presents some advantages relative to the transmission ofits binary digits. As a matter of fact, if ternary condition 1 isrepresented alternatively by the binary bits 00 and 11, there isobtained on an average equal numbers of 0 and 1 for transmission, whichis a very favorable condition to provide synchronization of thereceiving equipments.

In accordance with the present invention the nonlinear decoder forternary numbers can be used either as an expansion-decoder, or as adecoder associated with a compressor-coder circuit, the coding beingcarried out according to the well known process of feedback-comparisoncoding, such as described, for example, in the book Notes onAnalog-Digital Conversion by A. K. Susskin (MIT publication) pp. 5.54 to5.60.

A feature of the present invention is the provision of a ternary decoderhaving a nonlinear characteristic approximated by pluralityinterconnected straight line segments each having different slopescomprising: a ternary code group source, said group having n ternarydigits, where n is equal to an integer greater than one; first meanscoupled to the source responsive to the m most significant ternarydigits of the code group to produce a first signal indicative of theminimum voltage of one of the straight line segments within which thecode group is located, where m is equal to an integer less than n;second means coupled to the source responsive to at least the (nm) leastsignificant ternary digits of the code group to produce a second signalindicative of the position of the code group along the one of thesegments; and third means coupled to the first and second meansresponsive to the first and second signals to produce an analog signalrepresented by the code group.

The ternary numbers to be decoded comprise 2;: binary bits to representnumbers with n ternary digits. In accordance with the present inventionthe decoder delivers voltages having an average value Eel/2, where Ed isthe decoded voltage corresponding to the ternary number 3l. The decodercharacteristic curve is symmetrical with respect to the point af theabscissa Ed/2, and it comprises nine segments, each segment coveringtwenty-seven consecutive numbers, with the slopes of the two consecutivesegments being in a ratio of three. The three segments centered on bothsides of the voltage Ed/Z define three coding zones in which thequantizing step has a value of V, and the other zones, on both sides ofthe central zones, respectively, have 3V, 9V, and 27V volts as a valueof the quantizing step. The analog voltage corresponding to a given codeis obtained by carrying out the following operations: (a) determinationof a zone to which the code belongs by examining the four binary digitscorresponding to the two most significant digits of the ternary number:(b) generation of a pedestal voltage characterizing the amplitude of theanalog voltage corresponding to the first code of the zone or straightline segment in which the ternary number is located; (c) determinationof the position of the ternary number in its zone or straight linesegment by examining the digits that have not been used to determine thezone or straight line segment within which the code of number islocated, these digits representing the difference number between theconsidered code and the maximum code of the immediately lower zone orstraight line segments; ((1) generation of a position voltagerepresenting the decoded value of the difference number by using thequantizing step value assigned to the zone to which the number belongs;and (e) addition of the pedestal and position voltages.

Another feature of the present invention is the provision of anarrangement for adding the pedestal and position voltages (the first andsecond signals) including connecting simultaneously one or more currentgenerators at different injection points of the ladder attenuator havingan insertion loss of three per cell, the injection point being chosenaccording to the zone to which the ternary number or code group belongs.

BRIEF DESCRIPTION OF THE DRAWING The above mentioned and other featuresand objects of this invention will become more apparent by reference tothe following description taken in conjunction with the accompanyingdrawings, in which:

FIGS. la to 1d illustrate symbols employed in the circuit of FIG. 3;

FIG. 2 illustrates the characteristic curve of the decoder according tothe principles of the present invention; and

FIG. 3 is a block diagram of the decoder in accordance with theprinciples of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Before describing the invention,the logical algebra notations will be discussed that are employed hereinin order to simplify the description of the logical operations. Thesubject is treated extensively in numerous papers and in particular inthe book Logical Design of Digital Computers by M. Phister (I. Wileypublisher).

Thus, if a condition characterized by the presence of a signal iswritten A, the condition characterized by the absence of said signalwill be written K.

These two conditions are linked by the well known logical relation AZ=0, in which the sign X is the symbol of the coincidence logicalfunction or AND function.

If a conditioner C appears only if the condition A and B aresimultaneosuly present, the logical function is written A B=C and thisfunction may be carried out by means of a coincidence or AND gate.

If a conditioner C appears when at least one of two conditions E and Fis present, the logical function is written E+F=C and this function iscarried out by means of a mixing gate or OR gate.

If one characterizes the condition A by the digit 1 and the condition Kby the digit 0, the condition B by the digit 1 and the condition 1' bythe digit 0, the combination A B may be written 11, the combination ZXBmay be written 01, etc.

Referring to FIG. 1, the meaning of some symbols used in FIG. 3 will bedescribed. FIG. la represents a simple AND gate. FIG. lb represents abistable circuit or flip-flop to which a control signal is applied overone of its input terminals 92-1 or 920 in order to set it in the 1 stateor to reset it in the 0 state. A voltage of same polarity as that of thecontrol signal is present, either on the output 93-1 when the flip-flopis in the 1 state, or on the output 93-0 when it is in the 0 state. Ifthe flip-flop is referenced B1, the logical condition whichcharacterizes the fact that it is in the 1 state will be written B1 andthat characterizing the fact that it is in the 0 state will be writtenBI. FIG. 10 represents a decoder which, in the case of the example,transforms a four-bit binary code group applied over the group ofconductors 94a into a 1 out of 16 codes, so that a signal appears ononly one among the sixteen conductors 94b for each one of the codegroups applied at the input. FIG. 1d represents a current generator 95controlled by a signal applied to its input terminal 96 and which isloaded by the resistor 97. If I designates the unit current, generator95 delivers a current 21 which is symbolized bylthe digit 2 placedinside the lower circle of the symbe.

At last, in a ternary number, a digit of rank 1 is considered the mostsignificant digit of the number, a digit of rank 2 is considered thenext less significant digit, etc. Similarly, when the ternary number isbinary coded with two bits per ternary rank the two most significantbits will be called pair of bits of rank 1, etc.

FIG. 2 illustrates the characteristic curve e=f(N) of the decoderaccording to the invention to which are applied ternary numbers Ncomprising at least two digits and which delivers voltages the averagevalue of which, in the case of sine wave voltages, is equal to Ed/Z, andthe peak amplitude of which is equal to nun 2 2 By way of a non-limitingexample, a decoder will be described for ternary numbers with n-fivedigits (3 =243 different code groups) comprising nine coding zones orinterconnected straight line segments and four slopes of diiferentvalues, each zone including twenty-seven ternary numbers.

There is represented, on the ordinate axis, the references of these ninezones and, between brackets, the two most significant ternary digitsthat characterize each one of these zones. The abscissae axis representsthe range of decoded voltages corresponding to these various zonesexpressed in quantizing units of amplitude V. It will be noticed that,as a consequence of the utilization of a ternary code, the zone C0 iscentered on both sides of the coordinate origin 0.

The characteristic curve of this decoder presents a multilinear shape,as it is constituted by a succession of straight line segments ofdifferent slopes.

The table I groups all the informations relative to the in register RG.This circuit comprises a ladder attenuator fed by current generators,the mode of operation of which is described in the US. Pat. No.3,298,017. These generators are controlled selectively by means of thesignals delivered by circuits PC and LD.

As a ternary code is used, each cell of the attenuator must bring anattenuation a that is an integer power of three. In this decoder u=3 =3which is obtained by taking the following values for the resistors:extreme shunt resistors=R; other shunt resistors=3R/2 and seriesresistors =2R. The characteristic impedance of the attenuator is thenequal to 3R/4.

It results that, if a current i is injected at point Q0, a voltageVx=3Ri/4 appears between point X and the ground and that, if theinjection point is shifted towards d 1fier.ent and t charactenstlc ofthe the left, the voltage Vx decreases each time in a ratio f ig f mgltoig d 1 her from of three. It is thus seen that this attentuation ratiois a 0 t co f :base negative power of three, the exponent of which isgiven 0 an elf equwa S e ema y n g by the digit of the reference of theinjection point. Thus, the values 0, 1 and 2 being assigned to the threeternary a current in ected at point Q2 produces a voltage attenudigrts.The column 3 indicates the correspondmg value at d ith e no th r nt ofthe pairs of binary bits Bla-Blb (rank 1) and B2a- 1 a W resp c e Samecu re B21) (rank 2) in ected at point Q0.

The column 4 indicates the references of the zones de- Moreover If at agwen 9 r t are mleclfed fined by the decoding of the correspondingbinary bits lrvered by two generators having a high internal reslstanceof column 3. The column 5 indicates the slope of the respect to theCharacteristic impedanee, there is l characteristics (in volts by code)in each one of these dltloh 0f the Currents and the Output Voltages dohhzones. The column 6 indicates the number of quantizing We W111 firstStudy, In felatlon Wlth the Process unit steps V (in hort; EQ) in a h zoTh ol used for the determination of the pedestal voltages, the 7indicates the fraction of Ed voltage range occupied by number stored inthe flip flops of register RG (FIG. 3) each one of the nine zones. beingexpressed in column 3, Table I.

TABLE I Number Code A of EQ Decimal Ternary in the Fraction NumberNumber 13141 El!) B2a B21) Zones Slope zone of E 0 0 0 1 0 1 0'4 27V 729as 0 1 0 1 0 0 0'3 9V 243 as 0 2 0 1 1 0 02 3V s1 ,41 1 0 0 0 0 1 0'1 v27 th 1 1 0 0 0 0 00 V 27 l-t 1 2 0 0 1 0 (W1 V 27 m 2 0 1 0 0 1 (W2 3V81 1- 21 2 1 1 0 0 0 0'3 91v 243 6 2 2 1 0 1 0 0'4 27v 729 ,s

Norm-Total number of quantizing steps: 2187.

FIG. 3 illustrates the block diagram of the decoder ac- The decodedvoltages corresponding to the twenty-seven cording to the presentinvention which comprises shift codes of the zone 04 are disposedbetween zero volts for register RG, zone decoder ZD, pedestal (firstsignal) the code, the decimal equivalent of which is zero, and signalgenerator PC, position (second signal) signal gen- 729V27V=702V for thecode, the decimal equivalent erator LD, and weighting and summingcircuit WR. of which is 3 1=26. These decoded voltages are posi-Register RG comprises flip flop Bla, Blb BSu, tion voltages generated,as will be seen further on, under B5b for the storage of the ten binarybits representing a the control of the signals delivered by circuit LD.S-digit ternary code. 1 h 0 d 1 f 1For ;h8h1 n}1m6d;%t617hlbgi116f code,thendecirgal equiv- Zone decoder ZD is coup ed to t e outputs an o a ento w ic is e onsas we as t e twentythe flip-flops of ternary rank 1 and 2(the In most signifisix following codes-to zone C 3. Therefore, theposition cant ternary digits) and delivers the zone signals O1 tovoltage is replaced by a pedestal voltage Ua=729V that C'4, C1 to 0'4,C0 to C4; all of these signals being is equal to the position voltagecharacterizing the number availableon the groups of conductors C. 26plus a quantizing step of the zone G4, which makes It will be noticedthat in logical notation: 27V. For the followlng codes of the zone C3there is added to this voltage Ua, position voltages having an Camplitude proportional to the position of the code in this zone and tothe value of the quantizing step.

Pedestehsignal generator PC dehvers Pedestal slghal This pedestalvoltage is kept for all the zones correscharacterrzmg the lower decodedvoltage of the coding Pending to higher numbers and every time the Zonezone to which the code stored in reglster RG belongs. changes, a newpedestal Voltage 1, U6 Uh is added Position Signal eg LD delivers a p gzl l which corresponds to the amplitude of the voltage covered agecontrol signal at is function on one ban of e b h i -U Zone eodihg Zone,and 011 the other hand of t l g of Table II represents the differentpedestal voltages used. number Constituted y the digits of ternary Ian3, 4 an It comprises the lines 1, 2, 3 and columns c indicating 5 1eastSignificant teThaTY digits) Stored in the value-in quantizing unitstepsof each pedestal voltister RG. age, the reference characters Ua toUh of these voltages Weighting and summing circuit WR delivers on itsoutand the reference characters of the pedestal control sigput X avoltage characterizing the value of the code stored nals P01 to P12generated by circuit Pc.

Table II also comprises columns a and b, respectively, indicating thenine coding zones and the four most significant binary bits whichcharacterize said zone.

The pedestal control signals generated for a given zone are indicated bythe crosses aligned on the corresponding line. Thus, for the zone C, thesignals P01, P11, P21 and P31 are simultaneously present.

The conditions for generation of these signals are immediately deducedfrom the Table II and are grouped in Table III which indicates all thelogical conditions in circuit PC (FIG. 3).

It will be noticed that the two digits of the reference characters ofthese pedestal signals characterize by the first digit the number of theinjection point of the current in the ladder attenuator (circuit WR,FIG. 3) and by the second digit a serial number distinguishing thesignals that control different current generators connected to the sameinjection point.

TABLE III Signal: Logical condition P01 C'3+C'2+F13 P11 c'zrfir P21 PEP31 Co+C" P32 (3" P33 131 P22 c"3+c"4 P12 0'4 0'' c"1+c"z+c"3+c"4Moreover, in order to simplify FIG. 3, the current generators have notbeen designed by particular reference characters and, later on, theywill be identified by the reference characters of their control signals.

lfIow let us consider the mode of generation of the pos tion voltagethat characterized the position of a code in 1ts zone, this voltagebeing added up, in the ladder attenuator, to the pedestal voltage.

It will be first assumed that, the ternary conditions 0, 1 and 2correspond, respectively, to currents O, I and 2I.

Thus, the decoding of the ternary digits of rank 3, 4 and correspondingto the twenty-seven codes of a zone gives the values of currentmentioined in Table IV. It should be noted that the codes belonging to agiven zone have the same digit of rank 2 and that their three lastdigits constitute one of the ternary numbers disposed between 000 and222.

If it is assumed that these codes belong to the zone 0 G4 (FIG. 2) andusing the highest quantizing step value, the current corresponding tothe digit of tenary rnak 3 will be injected at point Q0, and thosecorresponding to the digits of rank 4 and 5 will be, respectively,injected at points Q1 and Q2. For the code 0222, the voltage at output Xwill be proportional to 1. 2I+ and, for the immediately higher code, itmust be proportional to since 1/9 represents the current quantum forthis zone.

' TABLE IV Ternary Number The generator delivering the pedestal voltageUa (see Table II) must, therefore, deliver a current of amplitude 31that is injected at point Q0. All the other pedestal currents have thesame value and are injected at the points defined by the first digit ofthe reference character of each current generator (Table II,'line 3 andTable III).

Since the value of the quantizing step varies in a ratio three betweentwo adjacent zones, the injection points of the position currentgenerators are shifted by one unit when passing from one zone to theadjacent zone, except for the zones C1 and Co which have the samequantizing step value-as it can be seen on Table V.

In this table, each rectangle indicated the pairs of current generatorsused in the production of the position voltage for the different zones,the corresponding control signals being delivered by circuit LD (FIG.3). It will be noticed that, for each ternary rank, there must be twocurrent generators for the decoding of the pair of binary bits thatrepresents it.

invention as set forth in the objects thereof and in the accompanyingclaims.

We claim:

1. A ternary decoder having a nonlinear characteristic approximated by aplurality of interconnected straight line segments each having differentslopes comprising:

a ternary code group source, said group having n ternary digits, where nis equal to an integer greater than one;

first means coupled to said source responsive to the ternary conditionof each of the m most significant ternary digits of said code group toproduce a first signal indicative of the minimum voltage of one of saidsegments within which said code group is located, where m is equal to aninteger less than n;

second means coupled to said source responsive to the Circuit LDreceives on one hand the Zone signals C and on the other hand signalscharacterizing the condition of the digits of ranks 3, 4 and 5 asdelivered by register RG.

The binary informations stored in the flip flops R301 to BSb are notdirectly used for the generation of the position signals. Thus,consider, for example, flip flops B3a and B3b, it is seen: for the pairof binary bits 01 (ternary digit condition (0), the logical conditionEfixfii; is obtained; for the pair of binary bits 00 (ternary digitcondition 1), the logical condition mxm is obtained; and for the pair ofbinary bits (ternary) digit condition 2), the logical condition z3a z3bis obtained.

It results that, if the signals z3b and z3a are applied to the controlinput of two current generators connected to the same injection pointand supplying, respectively, current of value I and 21, there will beobtained currents proportional to the coded ternary digit.

Table VI indicates the logical conditions for generation, in circuit LD,of the position voltage control signals corresponding to the shiftingshown in the Table V.

While we have described above the principles of our invention inconnection with specific apparatus, it is to be clearly understood thatthis description is mode only by way of example and not as a limitationto the scope of our ternary condition of each of the (nm) leastsignificant ternary digits of said code group to produce a second signalindicative of the position of said code group along said one of saidsegments; and third means coupled to said first and second meansresponsive to said first and second signals to produce an analog signalrepresented by said code group. 2. A decoder according to claim 1,wherein: said third means includes:

a weighting and summing circuit. 3. A decoder according to claim 2,wherein: said weighting and summing circuit includes:

a weighted ladder attenuator having a plurality of input points and anoutput, and plurality of difierently weighted current generators coupledto each of said input points and at least one of said first and secondmeans, appropriate ones of said current generators being activated by atleast one of said first and second signals to produce at said outputsaid analog signal. 4. A decoder according to claim 1, wherein: saidfirst means includes:

fourth means coupled to said source responsive to the ternary conditionof said most significant ternary digits to produce a third signalidentifying said one of said segments, and fifth means coupled to saidsource and said fourth means responsive to the ternary condition of themost significant ternary digit and said third signal to produce saidfirst signal. 5. A decoder according to claim 4, wherein: said secondmeans includes:

sixth means coupled to said source and said fourth means responsive tothe ternary condition of said least significant ternary digits and saidthird signal to produce said second signal. 6. A decoder according toclaim 5, wherein: said third means includes:

a weighted ladder attenuator having a plurality of input points and anoutput, and a plurality of differently weighted current generatorscoupled to each of said input points and at 1 1 least one of said fifthand sixth means, appropriate ones of said current generators beingactivated by at least one of said first and second signals to produce atsaid output said analog signal. 7. A decoder according to claim 1,wherein: each ternary condition of each of said ternary digits isrepresented by a different pair of binary digits; and said sourceincludes:

a shift register having n pairs of binary devices, each of said pairs ofbinary devices storing said pair of binary digits representing theternary condition of one of said ternary digits. 8. A decoder accordingto claim 7, wherein: said first means includes:

fourth means coupled to m pairs of said binary devices representing theternary conditions of said m most significant ternary digits to producea third signal identifying said one of said segments, and fifth meanscoupled to said fourth means and said pair of binary devicesrepresenting the ternary condition of the most significant ternary digitto produce said first signal. 9. A decoder according to claim 8,wherein: said second means includes:

sixth means coupled to said fourth means and (nm) pairs of said binarydevices representing the ternary conditions of said (nm) leastsignificant ternary digits to produce said second signal, 10. A decoderaccording to claim 9, wherein: said third means includes:

a weighted ladder attenuator having a plurality of input points and anoutput, and a plurality of differently weighted current generatorscoupled to each of said input points and at least one of said fifth andsixth means, appropriate ones of said current generators being activatedby at least one of said first and second signals to produce at saidoutput said analog signal.

References Cited UNITED STATES PATENTS 3,290,671 12/1966 Lamoureux340-347 3,382,438 5/:1968 Geller 340347 3,305,857 2/1967 Barber 340-3473,298,017 l/l967 Avignon 340347 25 MAYNARD R. WILBUR, Primary ExaminerJ. GLASSMAN, Assistant Examiner

